1. Field of the Invention
The present invention relates to a MOS type solid-state imaging device. In particular, the present invention relates to a solid-state imaging device using an amplification type MOS sensor.
2. Description of the Related Art
In recent years, a MOS type solid-state imaging device using an amplification type MOS sensor has been practically utilized as one of solid-state imaging devices. This solid-state imaging device amplifies a signal detected by a photo diode on a cell by cell basis by means of a MOS transistor, and is featured by high sensitivity.
A configuration of cells (pixels) of the MOS type solid-state imaging device is made of: a photo diode for photoelectric conversion; a readout transistor for reading out a signal; an amplifier transistor for amplifying a signal; a vertical selector transistor for selecting a readout line; and a reset transistor for resetting a signal charge or the like. In addition, a source of the amplifier transistor is connected to a vertical signal line so that a signal outputted to the vertical signal line is outputted to a horizontal signal line via a vertical selector transistor (refer to Jpn. Pat. Appln. KOKAI Publication No. 2000-150848, for example).
In the meantime, in the solid-state imaging device of this type, four transistors, i.e., a readout transistor, an amplifier transistor, a vertical selector transistor, and a reset transistor are included in one pixel. Thus, if the pixel is reduced in size for the purpose of achieving multiple pixels, an area of a photo diode is reduced in size. Thus, there has been a problem that a saturation signal having pixel features decreases, and optical shot noise becomes high.
This problem will be described with reference to a plan view of one pixel in a conventional MOS type solid-state imaging device shown in FIG. 10. In FIG. 10, reference numeral 50 denotes a photo diode; reference numeral 51 denotes a signal detector section; reference numeral 52 denotes a signal scanning circuit region; reference numeral 53 denotes a gate of a readout transistor; reference numeral 54 denotes a gate of an amplifier transistor; reference numeral 55 denotes a gate of a vertical selector transistor; reference numeral 56 denotes a gate of a reset transistor; reference numeral 57 denotes a source drain contact; reference numeral 58 denotes a contact on a gate; reference numeral 59 denotes an element isolating region. Wiring connections are not shown because they include a variety of combinations.
As shown in FIG. 10, in a conventional pixel, all of the contacts to gates 53, 54, 55, and 56 of each transistor have been obtained on the element isolating region 59. This is a process rule which is similar to a logic. That is, in the logic process, when a contact is disposed on an active region of a transistor, “gm” and a current drive capability are degraded. Thus, it is believed to be undesirable to form a contact on an active region of a transistor. It is general to employ such a configuration in an element other than a logic.
As described above, in the conventional MOS type solid-state imaging device, a gate contact of a transistor of a signal scanning circuit section is obtained on an element isolating region so that an area of the element isolating region cannot be reduced in size so much. As a result, there has been a problem that a photo diode area, in particular, a light receiver area is reduced in size, and optical shot noise becomes high.